Exposed wire-bonded chip package with gold contacts, photographed in our laboratory

IMSE-CNM

Trusted Systems-on-Chip based on CMOS and integrated photonics technologies

We design secure systems-on-chip and integrated photonics, from transistor-level primitives to trustworthy die-to-die communication.

RISC-V | PUFs | TRNGs | Side-channel security | Photonic ICs

Explore our research About the group

Wire-bonded chip package
HWSec-CSIC laboratory photographPhoto: Juan Carlos Ortiz (CSIC Andalucía)

Research areas

View all projects

From devices to systems

We investigate security at multiple levels, combining hardware design, cryptography and photonics.

SPIRS evaluation board with a socketed chip and external connectors

Secure SoCs
on RISC-V

Secure architectures and cryptographic primitives for embedded systems, with protection against physical attacks.

Close-up of an exposed die and bond wires inside a chip package

Physical security
primitives

PUFs, TRNGs and hardware mechanisms for unclonable identities, robust randomness and secure key management.

Optical fibres held by precision alignment stages on a laboratory bench

Integrated photonics
for security

Photonic devices and hybrid approaches to secure identities, communication and cryptographic mechanisms.

SPIRS board connected to measurement probes and ribbon cables

Open die-to-die
communication

Open frameworks and methods for trustworthy communication between chiplets in heterogeneous systems.

Photography · SPIRS: Juan Carlos Ortiz (CSIC Andalucía) · Photonics: Sofía Villar (IMSE-CNM)

Featured research

Red CW305 FPGA target board with coaxial connections and an attached evaluation board — CW305 FPGA evaluation hardware · laboratory photograph.Photo: Sofía Villar (IMSE-CNM)

Authenticated encryptionHardware implementationSide-channel protection

The International Conference on Availability, Reliability and Security (ARES 2026) · 2026

ChaCha20-Poly1305

Towards a Side-Channel-Resistant and Scalable ChaCha20-Poly1305 Hardware Implementation

F. J. Rubio-Barbero, P. Navarro-Torrero, E. Camacho-Ruiz, M. C. Martínez-Rodríguez, P. Brox

Research into scalable ChaCha20-Poly1305 hardware and side-channel resistance for authenticated encryption, presented at ARES 2026.

View source View all publications

RO-PUF/TRNG characterization setup from Figure 15: development board (1), power supplies (2), and temperature control system (3). — Figure 15. RO-PUF/TRNG characterization under voltage and temperature variations.Luis F. Rojas-Muñoz, Santiago Sánchez-Solano, Macarena C. Martínez-Rodríguez and Piedad Brox. Original article · CC BY 4.0 · Full-size figure

Physical securityPUFs and TRNGsLaboratory characterization

Sensors · 2023

RO-PUF/TRNG evaluation

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices

L.F. Rojas-Muñoz, S. Sánchez-Solano, M.C. Martínez-Rodríguez, P. Brox

On-line evaluation and monitoring of an RO-based PUF/TRNG for IoT devices, including laboratory characterization under voltage and temperature variations.

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Scheduling strategy for K-PKE.KeyGen in ML-KEM-512, reproduced from Figure 6 of the HOPE-MLKEM paper. — Figure 6. Example scheduling strategy for K-PKE.KeyGen in ML-KEM-512.Eros Camacho-Ruiz, Pablo Navarro-Torrero and Alejandro Cabrera Aldaya. Original article · CC BY 4.0 · Full-size figure

Post-quantum cryptographyML-KEMSide-channel protection

IACR Transactions on Cryptographic Hardware and Embedded Systems · 2026

HOPE-MLKEM

A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM

E. Camacho-Ruiz, P. Navarro-Torrero, A. Cabrera Aldaya

A framework for designing high-order side-channel-protected ML-KEM hardware, illustrated by the paper’s scheduling strategy for K-PKE.KeyGen.

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SPIRS hardware evaluation board photographed in the laboratory — SPIRS evaluation board · laboratory context.Photo: Juan Carlos Ortiz (CSIC Andalucía)

KECCAKSecond-order maskingHardware security

Proceedings of the 23rd International Conference on Security and Cryptography (SECRYPT) · 2026

Second-order masked KECCAK

Efficient Second-Order Masked KECCAK Implementation without Online Fresh Randomness

Juan Manuel Moreno-Cenizo, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

An efficient second-order masked KECCAK hardware implementation that does not require online fresh randomness, presented at SECRYPT 2026.

Read paper Repository View all publications

Wire-bonded die inside a chip package, photographed in our laboratory — Wire-bonded device package · group photograph.Photo: Juan Carlos Ortiz (CSIC Andalucía)

65-nm CMOSRO-PUF

IEEE Open Journal of the Solid-State Circuits Society · 2026

Ring-oscillator PUFs in 65-nm CMOS

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation

P. Ortega-Castro, E. Camacho-Ruiz, J. M. Mora-Gutiérrez, P. Brox, M. C. Martínez-Rodríguez

A robust and scalable ring-oscillator PUF implementation in 65-nm CMOS, using the physical properties of silicon for hardware identity.

Read paper View all publications

Microscope above fibre alignment stages on an optical laboratory bench — Optical laboratory bench · group photograph.Photo: Sofía Villar (IMSE-CNM)

CryptoPICIntegrated photonics

AEI · Generación de Conocimiento · 1 Nov 2025 – 30 Oct 2028

CryptoPIC

Advanced security in Photonic Integrated Circuits

CryptoPIC investigates physically unclonable functions and cryptographic primitives in photonic integrated circuits.

Explore CryptoPIC View all publications

Active research areas: 4
Publications in the archive: 27
Ongoing research projects: 5

About us

Hardware security
at IMSE-CNM (CSIC)

The security of modern computing infrastructure relies on hardware. At HWSec-CSIC we explore advanced, open approaches to secure systems, including RISC-V architectures and integrated photonics.

We are based at the Instituto de Microelectrónica de Sevilla, a joint centre of CSIC and the Universidad de Sevilla.

Meet the team

HWSec-CSIC researchers outside the Instituto de Microelectrónica de Sevilla — HWSec-CSIC at the Instituto de Microelectrónica de Sevilla.

Recent publications

View all publications

2026

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation

P. Ortega-Castro, E. Camacho-Ruiz, J. M. Mora-Gutiérrez, P. Brox, M. C. Martínez-Rodríguez

IEEE Open Journal of the Solid-State Circuits Society

Link

Citation

Plain-text citation

P. Ortega-Castro, E. Camacho-Ruiz, J. M. Mora-Gutiérrez, P. Brox, M. C. Martínez-Rodríguez. Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation. IEEE Open Journal of the Solid-State Circuits Society, 2026. https://doi.org/10.1109/OJSSCS.2026.3689804

BibTeX

@article{ortegacastro2026d23c0b,
  author = {P. Ortega-Castro and E. Camacho-Ruiz and J. M. Mora-Gutiérrez and P. Brox and M. C. Martínez-Rodríguez},
  title = {{Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation}},
  journal = {IEEE Open Journal of the Solid-State Circuits Society},
  year = {2026},
  doi = {10.1109/OJSSCS.2026.3689804}
}

2026

Hardware-Rooted Device Identity for IoT: Integrating Silicon PUFs and DICE in RISC-V Embedded Systems

S. Sisinni, L. Ferro, E. Bravi, P. Navarro-Torrero, E. Camacho-Ruiz, M. C. Martínez-Rodríguez, P. Brox, A. Lioy

IEEE Access · Vol. 14

Link

Citation

Plain-text citation

S. Sisinni, L. Ferro, E. Bravi, P. Navarro-Torrero, E. Camacho-Ruiz, M. C. Martínez-Rodríguez, P. Brox, A. Lioy. Hardware-Rooted Device Identity for IoT: Integrating Silicon PUFs and DICE in RISC-V Embedded Systems. IEEE Access, vol. 14, 2026. https://doi.org/10.1109/ACCESS.2026.3674839

BibTeX

@article{sisinni20261c258d,
  author = {S. Sisinni and L. Ferro and E. Bravi and P. Navarro-Torrero and E. Camacho-Ruiz and M. C. Martínez-Rodríguez and P. Brox and A. Lioy},
  title = {{Hardware-Rooted Device Identity for IoT: Integrating Silicon PUFs and DICE in RISC-V Embedded Systems}},
  journal = {IEEE Access},
  year = {2026},
  volume = {14},
  doi = {10.1109/ACCESS.2026.3674839}
}

2026

A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM

E. Camacho-Ruiz, P. Navarro-Torrero, A. Cabrera Aldaya

IACR Transactions on Cryptographic Hardware and Embedded Systems · Vol. 2026 · No. 2 · pp. 272-295

Link

Citation

Plain-text citation

E. Camacho-Ruiz, P. Navarro-Torrero, A. Cabrera Aldaya. A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM. IACR Transactions on Cryptographic Hardware and Embedded Systems, vol. 2026, no. 2, pp. 272-295, 2026. https://doi.org/10.46586/tches.v2026.i2.272-295

BibTeX

@article{camachoruiz2026067c04,
  author = {E. Camacho-Ruiz and P. Navarro-Torrero and A. Cabrera Aldaya},
  title = {{A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM}},
  journal = {IACR Transactions on Cryptographic Hardware and Embedded Systems},
  year = {2026},
  volume = {2026},
  number = {2},
  pages = {272--295},
  doi = {10.46586/tches.v2026.i2.272-295}
}

Research projects

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ODE4EC-DIG

Ongoing

HORIZON JU Innovation Actions

1 Jul 2026 – 30 Jun 2029

ODE4EC-DIG aims to develop a complete, open-source Electronic Design Automation (EDA) flow for digital System-on-Chip (SoC) design, targeting advanced 65-28nm technology nodes.

Q-FENCE

Ongoing

Horizon Europe

1 Nov 2025 – 31 Oct 2028

A hybrid security framework combining classical, quantum and post-quantum cryptographic techniques to protect digital infrastructure.

DECIDE

Ongoing

Chips JU

1 Jan 2025 – 31 Dec 2028

A virtual chip design platform that broadens access to advanced semiconductor technologies for European startups, SMEs and research institutions.

Trusted Systems-on-Chip based on CMOS and integrated photonics technologies

From devices to systems

Secure SoCs
on RISC-V

Physical security
primitives

Integrated photonics
for security

Open die-to-die
communication

Featured research

Towards a Side-Channel-Resistant and Scalable ChaCha20-Poly1305 Hardware Implementation

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices

A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM

Efficient Second-Order Masked KECCAK Implementation without Online Fresh Randomness

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation

Advanced security in Photonic Integrated Circuits

Hardware security
at IMSE-CNM (CSIC)

Recent publications

Robust and Scalable Cell-Based 65-nm CMOS RO-PUF Implementation

Plain-text citation

BibTeX

Hardware-Rooted Device Identity for IoT: Integrating Silicon PUFs and DICE in RISC-V Embedded Systems

Plain-text citation

BibTeX

A Framework for designing High-Order Side-Channel Protected Hardware Implementations of ML-KEM

Plain-text citation

BibTeX

Research projects

ODE4EC-DIG

Q-FENCE

DECIDE

QUBIP

SQPRIM

GoIT

SPIRS

CryptoPIC

ARES

TECHNOQUANTUM

Trusted Systems-on-Chip based on CMOS and integrated photonics technologies

From devices to systems

Secure SoCson RISC-V

Physical securityprimitives

Integrated photonicsfor security

Open die-to-diecommunication

Featured research

Hardware securityat IMSE-CNM (CSIC)

Recent publications

Plain-text citation

BibTeX

Plain-text citation

BibTeX

Plain-text citation

BibTeX

Research projects

Secure SoCs
on RISC-V

Physical security
primitives

Integrated photonics
for security

Open die-to-die
communication

Hardware security
at IMSE-CNM (CSIC)